The Belgian Microelectronics Research Center first introduced a CMOS CFET device with stacked upper and lower source/drain contacts at the 2024 IEEE VLSI Technology and Circuit Symposium (VLSI 2024). Although the result was achieved by using frontal lithography on two contacts, IMEC also demonstrated the feasibility of moving the lower contact to the backside of the chip, thereby increasing the survival rate of the upper device from 11% to 79%.

IMEC's logic technology roadmap plans to introduce CFET technology in node A7, which, combined with advanced wiring technology, is expected to reduce the height of standard batteries to 4T or below without sacrificing performance.

The first demonstration of a functional monolithic CMOS CFET device with upper and lower contacts, 18 nm gate length, 60 nm gate channel, and 50 nm vertical spacing between N-type and P-type includes two specific CFET modules: intermediate dielectric isolation (MDI) and stacked lower and upper contacts.

The MDI module isolates the upper and lower doors, distinguishes the threshold voltage settings for N-type and P-type devices, and allows for the merging of internal partitions.

The second key module is to form the lower and upper contacts of the stacked source/drain, which are vertically separated by dielectric insulation. The key step is to fill and etch the bottom contact metal, and then fill and etch the medium, all within the same reduced space as the MDI stack.

Naoto Horiguchi believes that there are a series of challenges when developing lower contacts from the front, which may affect the resistance of lower contacts and limit the process window of upper equipment. We are currently conducting research to determine the optimal contact routing method.