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The FE2.1 is a highly integrated, high quality, highperformance, low power consumption, yet low costsolution for USB 2.0 High Speed 7-Port Hub.
It adopts Multiple Transaction Translator (MTT)architecture to explore the maximum possiblethroughput. Six, instead of two, non-periodictransaction buffers are used to minimize potentialtraffic jamming. The whole design is based on state-machine-control to reduce the response delay time;no micro controller is used in this chip.
To guarantee high quality, the whole chip is coveredby Test Scan Chain - include even on the high speed(480MHz) modules, so that all the logic componentscould be fully tested before shipping. Special Build-In-Self-Test mode is designed to exercise all high,full, and low speed Analog Front End (AFE)components in the packaging and testing stages aswell.
Low power consumption is achieved by using0.18um technology and comprehensive power/clockcontrol mechanism. Most part of the chip will notbe clocked unless needed.