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The ENC28J60 is designed to operate at 25 MHz with acrystal connected to the OSC1 and OSC2 pins. TheENC28J60 design requires the use of a parallel reso-nance crystal. Use of a series resonance crystal may givea frequency out of the crystal manufacturer specifications.A typical oscillator circuit is shown in Figure 2-1.
The ENC28J60 may also be driven by an external clocksource connected to the OSC1 pin as shown inFigure 2-2.

The ENC28J60 contains an Oscillator Start-up Timer(OST) to ensure that the oscillator and integrated PHYhave stabilized before use. The OST does not expireuntil 7500 OSC1 clock cycles (300 us) pass afterPower-on Reset or wake-up from Power-Down modeoccurs. During the delay, all Ethernet registers and buf-fer memory may still be read and written to through theSPI bus. However, software should not attempt totransmit any packets (set ECON1.TXRTS), enablereception of packets (set ECON1.RXEN) or access anyMAC, MIl or PHY registers during this period.
When the OST expires, the CLKRDY bit in the ESTATregister wil be set. The application software should pollthis bit as necessary to determine when normal deviceoperation can begin.

Ethernet Controller Features
.IEEE 802.3M Compatible Ethemet Controller
.Fully Compatible with 10/100/1000Base-T Networks
.Integrated MAC and 10Base-T PHY
.Supports One 10Base-T Port with AutomaticPolarity Detection and Correction
.Supports Full and Half-Duplex modes
.Programmable Automatic Retransmit on Collision
. Programmable Padding and CRC Generation
.Programmable Automatic Rejection of ErroneousPackets
.SPI Interface with Clock Speeds up to 20 MHz
Buffer
.8-Kbyte Transmit/Receive Packet Dual Port SRAM
.Configurable Transmit/Receive Buffer Size
.Hardware Managed Circular Receive FIFO
.Byte-Wide Random and Sequential Access withAuto-Increment
.Internal DMA for Fast Data Movement
Hardware Assisted Checksum Calculation forVarious Network Protocols
Medium Access Controller (MAC)Features
.Supports Unicast, Multicast and BroadcastPackets
.Programmable Receive Packet Filtering and Wake-upHost on Logical AND or OR of the Following:
- Unicast destination address
- Multicast address
- Broadcast address
-Magic PacketTM
- Group destination addresses as defined by64-bit Hash Table
- Programmable Pattern Matching of up to64 bytes at user-defined offset
Physical Layer (PHY) Features
.Loopback mode
.Two Programmable LED Outputs for LINK, TX,RX, Collision and Full/Half-Duplex Status

Operational
Six Interrupt Sources and One Interrupt Output Pin
25 MHz Clock Input Requirement
Clock Out Pin with Programmable Prescaler
Operating Voltage of 3.1V to 3.6V (3.3V typical)
5V Tolerant Inputs
Temperature Range: -40°C to +85°C Industrial,0°C to +70°C Commercial (SSOP only)
.28-Pin SPDIP, SSOP, SOIC, QFN Packages